`include "defines.v"
module if_id(
	input wire clk,
	input wire rst,
	input wire[5:0] pause, //流水线暂停信号
	input wire[31:0] if_pc,
	input wire[31:0] if_inst,
	output reg[31:0] id_pc,
	output reg[31:0] id_inst
);
	always@(posedge clk)
		if(rst == `RstEnable) 
		begin
			id_pc <= 0;
			id_inst <= 0;
		end
		else if(pause[1] == `PAUSE && pause[2] == `NO_PAUSE) //取指阶段暂停，译码阶段继续
		begin
			id_pc <= `ZeroWord;
			id_inst <= `ZeroWord;
		end
		else if(pause[1] == `NO_PAUSE)
		begin
			id_pc <= if_pc;
			id_inst <= if_inst;
		end
endmodule